Union IT Minister Ashwini Vaishnaw showcased India’s leap in semiconductor design at a global tech summit, unveiling a palm-sized model of a homegrown wafer capable of rivaling international market leaders.
Speaking at the summit, Vaishnaw emphasised India’s strides in digital-led growth, citing initiatives in digital credit, fast mobile data, and large language models (LLMs). “Data is the new oil,” he said. “Data centers are the new refineries. We must take control of our destiny and make sure that the talent we have in our country finds opportunities here.”
Highlighting India’s technological prowess, Vaishnaw noted that the nation now designs chips of 2 nanometres, down from earlier 5nm and 7nm models. “Earlier it used to be 5 nanometres, 7 nanometres. Now 2 nanometre chips are here; they are the most complex of chips, the smallest. Those are now designed in India,” he said.
To illustrate the intricacy of chip fabrication, Vaishnaw held up a wafer. “This is a wafer. On this, building a complete city which will have its own plumbing, its own heating, its own electrical network, its own circuits… it’s a very, very complex thing,” he explained.
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He described the scale of precision involved: “A chip can be extremely small, you can't even see it with a microscope. It's 10,000 times smaller than human hair. When the power supply went off for five minutes, it was a loss of $200 million. The chemicals and gases used are extremely pure, ultra-pure chemicals and gases, 500-plus chemical parts per billion purity.”
Vaishnaw also highlighted India’s talent base, stating that 20 per cent of the world’s design engineers are in India, giving the country a “unique strength” in advanced chip design.
The 2025 global tech summit, themed ‘Edge of the Unknown: Risk. Resolve. Renewal’, convened world leaders, innovators, and cultural icons to explore emerging challenges and opportunities in a rapidly evolving world.
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